1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Description of the Related Art
In recent years, as semiconductor devices have been highly integrated, circuit patterns of LSI devices contained therein have been increasingly made finer. Fine processing of the patterns requires not only thinner line widths simply but also improvements in dimensional accuracy and positional accuracy of patterns. Semiconductor memory devices called memories are not an exception. In memory cells formed with the free use of high-accuracy processing technologies, it has been continuously desired that a certain amount of charge required for storage is held within a narrower region.
Various memories such as DRAMs, SRAMs and flash memories have been produced up to now. These memories all use a MOSFET in a memory cell and accordingly fine processing of patterns causes a need for an improvement in dimensional accuracy at a higher rate than the rate of fine processing. Therefore, the lithography technology of forming these patterns is imposed with larger loads, which become a factor in increasing the lithography process cost that occupies the major part of the current mass production cost, that is, a factor in increasing the product cost (see Shinichiro Kimura, “Semiconductor memory; DRAM”, OYO BUTURI, 2000, Vol. 69, No. 10, pp. 1233 to 1240, and Natsuo Ajika, “Flash memory, recent trend”, OYO BUTURI, 2000, Vol. 69, No. 12, pp. 1462 to 1466).
As a technique overcoming such problems, a memory called ReRAM which has memory cells configured of selective elements including non-ohmic elements typified by diodes and a resistance changing material has been recently proposed. The ReRAM can be configured without using electric charge storage for holding memory and using no MOSFET for memory cells. The integration higher than the related-art trend is expected.
From the viewpoint of effective utilization of energy resources, the power consumption of semiconductor devices has been required to be minimized. This is not an exception for memories. The proportion of the memory cell array portion occupying the entire memory device is high. Therefore, it is important to reduce the power consumption of the memory cell array (see U.S. Pat. No. 6,504,753). In the ReRAM which uses no MOSFET for memory cells, not only the power consumption of the memory cell corresponding to an actually accessed bit, but also the power consumption of the remaining memory cells, cannot be neglected. The power consumption of the entire memory cell array has been required to be reduced.